One type of flash erasable and electrically programmable read-only memory ("flash EPROM") is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The prior flash EPROM can be programmed, and once programmed, the entire contents of the prior flash EPROM can be erased by electrical erasure. The prior flash EPROM may then be reprogrammed with new data.
One type of prior flash EPROM typically includes content addressable memory ("CAM") cells in addition to a main memory array. The CAM cells are typically used to perform certain configuration and management functions for the prior flash EPROM. The CAM cells typically comprise flash EPROM cells. The CAM cells can be programmed to configure the prior flash EPROM with respect to device operations (for example, data widths, latched inputs, the chip enable signal CEBTTL active high, the output enable signal OEBTTL active high, etc.). The CAM cells can also be used to activate (or deactivate) redundancy cells and reference cells with respect to the main memory array. The redundancy cells are used in place of defective cells of the main memory array. The CAM cells are programmed with the configuration information before the prior flash EPROM reaches the end user as a final product. Before the prior flash EPROM is shipped by the manufacture, a series of tests are conducted to determine whether the prior flash EPROM meets its device specifications. Typically, the tests involve testing different device configurations.
One disadvantage associated with this prior flash EPROM is that during testing of the prior flash EPROM, the CAM cells that store the configuration information of the prior flash EPROM need to be reprogrammed with various device configuration information for the testing. For example, when the prior flash EPROM can be configured as a byte wide flash EPROM or as a word wide flash EPROM and when a CAM cell is used to configure the prior flash EPROM with a byte wide data width, the CAM cell is first programmed with byte wide data width configuration information and the prior flash EPROM is then configured accordingly. During testing, however, the prior flash EPROM needs to be also tested under the word wide data width architecture. When this occurs, the CAM cell that stores the byte wide data width configuration information needs to be reprogrammed with the word wide data width configuration information. Typically, programming a CAM cell takes more time than just writing to a volatile register. When the prior flash EPROM is repeatedly tested between the word wide data width architecture and the byte wide data width architecture, the CAM cell needs to be repeatedly reprogrammed. This typically causes the test of the prior flash EPROM to be relatively long.
Moreover, because programming and reprogramming of a CAM cell typically requires additional external circuitry, it is typically very inconvenient and costly to repeatedly reprogram the CAM cell.